The present invention relates to video processing and more specifically to compensating for vertical droop in a video frame using a Linear Feedback Shift Register circuit without the need for using line memories.
Referring now to FIG. 1 a frame 102 of a video image is shown that is, for example 1600 pixels×1280 lines. Each line can include one to two thousands of pixels. The number of lines in a frame can also be one to two thousands. Ideally, for a uniform image value of 200, every pixel should have a value of 200. Due to offsets and mismatches in a given design, there will be droops both horizontally and vertically. As shown above, the vertical droop is one less for each of the sections A through D from top to bottom. The vertical droop can be compensated by adding offsets to each of the pixels. For example, pixels in zone B will have an added value of one, pixels in zone C will have an added value of two, and pixels in zone D will have an added value of three.
Referring now to FIG. 2 another typical frame 202 of a video image is shown. Another example of vertical droop compensation is shown for frame 202. As before, a pixel value is added to compensate for vertical droop in a given design. In the example of FIG. 2, an offset of ten is added in section A, an offset of eleven is added in section B, an offset of twelve is added in section C, and an offset of thirteen is added in section D.
With respect to the video frames shown in FIGS. 1 and 2, it is important to note that there will be vertical line artifacts due to this vertical droop compensation. Hence, dither has to be introduced to blur out these transitions from one section to another. It is also important to note that, for dither to be effective, the dither should be introduced over a few lines (maybe more than ten lines). A very blunt way to implement this dither is to have ten line memories to remember which pixels have been compensated. For each line, each pixel is compensated randomly. Finally all the pixels in the row are compensated after 10 lines.
A prior art circuit 300 for vertical dithering with line memories is shown in FIG. 3. Circuit 300 includes an LFSR 302 for generating a random sequence signal RND_SEQ. A plurality of line memories 304A, 304B, 304C, 304D, and 304E receives the RND_SEQ signal and a plurality of read/write signals WR1, WR2, WR3, WR4, and WR5. Each line memory generates an output sequence signal corresponding to signals SEQ1, SEQ2, SEQ3, SEQ4, and SEQ5 in FIG. 3. Each output sequence signal is gated with a corresponding AND gate 306A, 306B, 306C, 306D, or 306E. The gating signals for the AND gates are EN1, EN2, EN3, EN4, and EN5. The output of all of the AND gates is received by OR gate 308 to provide the CONTROL output signal.
In operation, the line memories are used to store one bit for each of the pixel to control whether to add an offset or not. While writing to line memory 304A (Line Memory 1), the RND_SEQ is also sent out as CONTROL as an offset control for the pixels. While writing to line memory 304B (Line Memory 2), the SEQ1 and RND_SEQ signals are also enabled to control the offset compensation. Similarly, while writing to line memory 304C (Line Memory 3), the SEQ1, SEQ2 and RND_SEQ signals are all enabled to control the offset compensation. This process is repeated for all line memories shown. While five line memories are shown, any number can be used.
While the circuit shown in FIG. 3, is effective for addressing for providing the required dithering, it uses line memories. These line memories can be large, which increases die size and cost.
What is desired is a dithering circuit for use in vertical droop compensation that eliminates the need for large line memories, reducing chip size and cost, and thereby increasing profit margins.